A major surface of an electronic circuit device--such as a silicon integrated-circuit chip or wafer, or a laser chip--typically has a two-dimensional array of solder bumps or "balls". Each of these bumps is situated on and contacts a separate metallic I/O (Input/Output) terminal of the chip ("chip terminal"). Quite often it is desired to electrically access each of these devices for testing them prior to their being assembled with a package, in order to avoid the cost of packaging defective devices. Thus, it is also desirable that the testing procedure itself does not destroy the device, i.e., that the testing should be nondestructive.
In one conventional nondestructive testing approach, known as "burn-in testing", the devices are tested under conditions of higher electrical and environmental stress--i.e., higher applied voltages and higher ambient temperatures--than would be encountered during normal subsequent operation in the package. Burn-in testing is carried out typically for a time duration in the range of one to ten hours or more. Also, testing for such time durations of electronic devices prior to assembly into packages is also desirable in some other contexts, i.e., in the absence of temperature or electrical stress (or of both).
U.S. Pat. No. 5,007,163 describes a method of nondestructive burn-in testing in which semiconductor integrated-circuit chips can be tested, one after the other, by means of temporary direct attachment of the terminals of each chip to metallic I/O pads of a testing substrate ("substrate pads"). Testing voltages (including power and ground) are applied to some of the chip terminals ("chip input terminals") via a set of wiring in the substrate connected to a set of the substrate pads ("substrate output pads") while the chip terminals and the substrate pads are pressed together under low pressure and while an electrically conductive liquid eutectic joint is formed at room temperature between each of the chip terminals and each of the respective substrate pads. In response to these applied testing voltages, response voltages are developed at other of the chip pads ("chip output terminals"), and these response voltages are measured via another set of wiring in substrate connected to another set of the substrate pads ("substrate input pads"). The eutectic joint remains liquid throughout the electrical testing. Preferably the eutectic is gallium/indium.
After the testing has been completed, the chip pads and the substrate pads are pulled apart, and eutectic material residue remaining on the chip terminals and/or the testing substrate pads is removed, for such residue would interfere with proper (multiple) contacts of the terminals of the next chip to be tested with the thus residue-coated substrate pads.
A disadvantage of the testing method described in the aforementioned patent is the need for removing any remaining eutectic residue, as well as the undesirably high electrical resistance of the liquid joint during testing.
In addition, with or without burn-in or other testing, it is desirable to have a method of bonding a semiconductor integrated circuit device or alternatively a laser device to a heat-sinking or heat-spreading element (submount) and, if desired, subsequently being able to remove the device from the submount, as for the purpose of reusing the submount for supporting another device, or in the alternative, if desired, to allow the device to remain bonded to the submount, as for the purpose of operating the device with the submount but without the need for further processing of the bonding. That is to say, it is desirable to have a method of bonding that can be subsequently temporary or permanent, as is subsequently desired.